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mosel vitelic 1 V8DJX232BLT/v8dj232blt 2m x 32 high performance edo/fpm memory module preliminary V8DJX232BLT/v8dj232blt rev. 0.1 february 1999 features n 2m x 32-bit organization n V8DJX232BLT edo n v8dj232blt fpm n utilizes high performance 1m x 8 cmos drams n fast access times: 45, 50, 60 ns n low power dissipation n cas before ras refresh, ras only refresh, and hidden refresh capability n standard 72-lead single-in-line module n single 5 v 10% power supply n ttl interface description the V8DJX232BLT/v8dj232blt memory module is organized as 2,097,152 x 32 bits in a 72- lead single-in-line module. the 2m x 32 memory module uses 8 mosel-vitelic 1m x 8 drams. the x32 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. device usage chart operating temperature range organization module type access time (ns) power 2m x 32 simm 50 60 std 0 c to 70 c V8DJX232BLT/v8dj232blt pin configuration 1363772 1 vss 2 i/o1 3 i/o17 4 i/o2 5 i/o18 6 i/o3 7 i/o19 8 i/o4 9 i/o20 10 vcc 11 nc 12 a0 13 a1 14 a2 15 a3 16 a4 17 a5 18 a6 19 nc 20 i/o5 21 i/o21 22 i/o6 23 i/o22 24 i/o7 25 i/o23 26 i/o8 27 i/o24 28 a7 29 nc 30 vcc 31 a8 32 a9 33 ras 3 34 ras 2 35 nc 36 nc 37 nc 38 nc 39 vss 40 cas 0 41 cas 2 42 cas 3 43 cas 1 44 ras 0 45 ras 1 46 nc 47 we 48 nc 49 i/o9 50 i/o25 51 i/o10 52 i/o26 53 i/o11 54 i/o27 55 i/o12 56 i/o28 57 i/o13 58 i/o29 59 vcc 60 i/o30 61 i/o14 62 i/o31 63 i/o15 64 i/o32 65 i/o16 66 nc 67 pd1* 68 pd2* 69 pd3* 70 pd4* 71 nc 72 vss * default presence detect is nc, optional configurations are available. pin names name description a0?9 addresses i/o1?/o32 data inputs/outputs ras 0?as 3 row address strobes cas 0?as 3 column address strobes we write enable pd1?d4 presence detect v cc power supply (5v) v ss ground nc no connection
2 V8DJX232BLT/v8dj232blt rev. 0.1 february mosel vitelic V8DJX232BLT/v8dj232blt absolute maximum ratings* ambient temperature under bias................................ ?0 c to +80 c storage temperature (plastic)..... ?5 c to +125 c voltage on any pin except v cc relative to v ss .........................?.0 v to +7.0 v voltage on v cc relative to v ss .....?.0 v to +7.0 v data out current .......................................... 50 ma power dissipation V8DJX232BLT............................................. 3.5 w v8dj232blt ............................................... 4.5 w *note: operation above absolute maximum ratings can adversely affect device reliability. capacitance* t a = 25 c, f = 1.0mhz, v cc = 5 v 10%, v ss = 0 v *note: capacitance is samples and not 100% tested. symbol parameter min. max. unit c in input capacitance, address inputs 111 pf c in input capacitance, w 127 pf c (i/o) input/output capacitance, i/o1?/o32 17 pf c in(ras) input capacitance, ras 0, ras 2 32 pf c in(cas) input capacitance, cas 0?as 3 32 pf part number information mosel vitelic manufactured 8 number of components mem. family pwr. v 8 dj 2 32 b lt speed 50 ns 60 ns dm = 2-sided simm (tin lead, low profile) 1k refresh 8 depth blank = 5v blank = fpm dram soj mem. type x x = edo page mode 32 width package code device features edge connector pin names 1 vss 2 i/o1 3 i/o17 4 i/o2 5 i/o18 6 i/o3 7 i/o19 8 i/o4 9 i/o20 10 vcc 11 nc 12 a0 13 a1 14 a2 15 a3 16 a4 17 a5 18 a6 19 nc 20 i/o5 21 i/o21 22 i/o6 23 i/o22 24 i/o7 25 i/o23 26 i/o8 27 i/o24 28 a7 29 nc 30 vcc 31 a8 32 a9 33 ras 3 34 ras 2 35 nc 36 nc 37 nc 38 nc 39 vss 40 cas 0 41 cas 2 42 cas 3 43 cas 1 44 ras 0 45 ras 146nc 47 we 48 nc 49 i/o9 50 i/o25 51 i/o10 52 i/o26 53 i/o11 54 i/o27 55 i/o12 56 i/o28 57 i/o13 58 i/o29 59 vcc 60 i/o30 61 i/o14 62 i/o31 63 i/o15 64 i/o32 65 i/o16 66 nc 67 pd1 68 pd2 69 pd3 70 pd4 71 nc 72 vss
mosel vitelic V8DJX232BLT/v8dj232blt 3 V8DJX232BLT/v8dj232blt rev. V8DJX232BLT/v8dj232blt functional diagram ras cas i/o 1 i/o 2 i/o 3 i/o 4 we oe v53c808h v53c808h v53c808h v53c808h v53c808h v53c808h v53c808h v53c808h c x ras 0 cas 0 a 0 ? 9 a 0 ? v cc gnd we ras cas i/o 1 i/o 2 i/o 3 i/o 4 we oe a 0 ? 9 cas 1 ras cas i/o 1 i/o 2 i/o 3 i/o 4 we oe a 0 ? 9 cas 2 ras 2 ras cas i/o 1 i/o 2 i/o 3 i/o 4 we oe a 0 ? 9 cas 3 ras cas i/o 1 i/o 2 i/o 3 i/o 4 we oe a 0 ? 9 ras 1 ras cas i/o 1 i/o 2 i/o 3 i/o 4 we oe a 0 ? 9 ras 3 ras cas i/o 1 i/o 2 i/o 3 i/o 4 we oe a 0 ? 9 ras cas i/o 1 i/o 2 i/o 3 i/o 4 we oe a 0 ? 9 dq 4 dq 7 dq 6 dq 7 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 24 dq 25 dq 27 dq 28 dq 29 dq 30 dq 31 dq 32 dq 33 dq 34 dq 0 dq 1 dq 2 dq 3 vcc gnd
4 V8DJX232BLT/v8dj232blt rev. 0.1 february mosel vitelic V8DJX232BLT/v8dj232blt dc and operating characteristics t a = 0 c to 70 c, v cc = 5 v 10%, v ss = 0 v, unless otherwise specified. symbol parameter access time V8DJX232BLT unit test conditions notes min. typ. max. i li input leakage current (any input pin) ?0 40 m av ss v in v cc i lo output leakage current (for high-z state) ?0 40 m av ss v out v cc ras , cas at v ih i cc1 v cc supply current, operating 50 580 ma t rc = t rc (min.) 1, 2 60 540 i cc2 v cc supply current, ttl standby 8 ma ras , cas at v ih other inputs 3 v ss i cc3 v cc supply current, ras -only refresh 50 580 ma t rc = t rc (min.) 2 60 540 i cc4 v cc supply current, edo page mode operation 50 340 ma minimum cycle 1, 2 60 320 i cc5 v cc supply current, standby, output enabled 8 ma ras = v ih , cas = v il other inputs 3 v ss 1 i cc6 v cc supply current, cmos standby 8 ma ras 3 v cc ?0.2 v, cas 3 v cc ?0.2 v, all other inputs 3 v ss i cc7 self refresh current 1.6 ma cbr cycle with t ras 3 t rass (min.) and cas = v il ; we = v cc ?.2v; a0?8 and d in = v cc ?.2v v cc supply voltage 4.5 5.0 5.5 v v il input low voltage ? 0.8 v 3 v ih input high voltage 2.4 v cc + 1 v 3 v ol output low voltage 0.4 v i ol = 2 ma v oh output high voltage 2.4 v i oh = ? ma
mosel vitelic V8DJX232BLT/v8dj232blt 5 V8DJX232BLT/v8dj232blt rev. dc and operating characteristics t a = 0 c to 70 c, v cc = 5 v 10%, v ss = 0 v, unless otherwise specified. symbol parameter access time v8dj232blt unit test conditions notes min. typ. max. i li input leakage current (any input pin) ?0 40 m av ss v in v cc i lo output leakage current (for high-z state) ?0 40 m av ss v out v cc ras , cas at v ih i cc1 v cc supply current, operating 50 840 ma t rc = t rc (min.) 1, 2 60 800 i cc2 v cc supply current, ttl standby 16 ma ras , cas at v ih other inputs 3 v ss i cc3 v cc supply current, ras -only refresh 50 840 ma t rc = t rc (min.) 2 60 800 i cc4 v cc supply current, fast page mode operation 50 400 ma minimum cycle 1, 2 60 360 i cc5 v cc supply current, standby, output enabled 8 ma ras = v ih , cas = v il other inputs 3 v ss 1 i cc6 v cc supply current, cmos standby 8 ma ras 3 v cc ?0.2 v, cas 3 v cc ?0.2 v, all other inputs 3 v ss v cc supply voltage 4.5 5.0 5.5 v v il input low voltage ? 0.8 v 3 v ih input high voltage 2.4 v cc + 1 v 3 v ol output low voltage 0.4 v i ol = 4.2 ma v oh output high voltage 2.4 v i oh = ? ma
6 V8DJX232BLT/v8dj232blt rev. 0.1 february mosel vitelic V8DJX232BLT/v8dj232blt ac characteristics t a = 0 c to 70 c, v cc = 5 v 10%, v ss = 0v unless otherwise noted ac test conditions, input pulse levels 0 to 3v # symbol parameter v8dj232blt unit notes 50 60 min. max. min. max. 1t ras ras pulse width 50 75k 60 75k ns 2t rc read or write cycle time 90 110 ns 3t rp ras precharge time 30 40 ns 4t csh cas hold time 50 60 ns 5t cas cas pulse width 14 15 ns 6t rcd ras to cas delay 19 36 20 43 ns 7t rcs read command setup time 0 0 ns 4 8t asr row address setup time 0 0 ns 9t rah row address hold time 9 10 ns 10 t asc column address setup time 0 0 ns 11 t cah column address hold time 7 10 ns 12 t rsh (r) ras hold time (read cycle) 14 15 ns 13 t crp cas to ras precharge time 5 5 ns 14 t rch read command hold time referenced to cas 0 0 ns 5 15 t rrh read command hold time referenced to ras 0 0 ns 5 16 t roh ras hold time referenced to oe 10 10 ns 17 t oac access time from oe 14 17 ns 18 t cac access time from cas 14 17 ns 6, 7 19 t rac access time from ras 50 60 ns 6, 8, 9 20 t caa access time from column address 24 30 ns 6, 7, 10 21 t lz cas to low-z output 0 0 ns 16 22 t hz output buffer turn-off delay time 0 8 0 10 ns 16 23 t ar column address hold time from ras 40 45 ns 24 t rad ras to column address 14 26 15 30 ns 11 delay time 25 t rsh (w) ras or cas hold time in write cycle 14 15 ns 26 t cwl write command to cas lead time 14 15 ns 27 t wcs write command setup time 0 0 ns 12, 13 28 t wch write command hold time 7 10 ns 29 t wp write pulse width 7 10 ns
mosel vitelic V8DJX232BLT/v8dj232blt 7 V8DJX232BLT/v8dj232blt rev. 30 t wcr write command hold time from ras 40 45 ns 31 t rwl write command to ras lead time 14 15 ns 32 t ds data in setup time 0 0 ns 14 33 t dh data in hold time 7 10 ns 14 34 t woh write to oe hold time 8 10 ns 14 35 t oed oe to data delay time 8 10 ns 14 36 t rwc read-modify-write cycle time 130 170 ns 37 t rrw read-modify-write cycle ras pulse width 87 105 ns 38 t cwd cas to we delay 34 40 ns 12 39 t rwd ras to we delay in read-modify-write cycle 68 85 ns 12 40 t crw cas pulse width (rmw) 52 65 ns 41 t awd col. address to we delay 42 58 ns 12 42 t pc fast page mode read or write cycle time 28 40 ns 43 t cp cas precharge time 7 8 ns 44 t car column address to ras setup time 24 30 ns 45 t cap access time from column precharge 27 34 ns 7 46 t dhr data in hold time referenced to ras 40 50 ns 47 t csr cas setup time cas -before-ras refresh 10 10 ns 48 t rpc ras to cas precharge time 0 0 ns 49 t chr cas hold time cas -before-ras refresh 12 15 ns 50 t pcm fast page mode read-modify-write cycle time 70 85 ns 51 t t transition time (rise and fall) 3 50 3 50 ns 15 52 t ref refresh interval (1024 cycles) 16 16 ms # symbol parameter v8dj232blt unit notes 50 60 min. max. min. max. ac characteristics (cont.)
8 V8DJX232BLT/v8dj232blt rev. 0.1 february mosel vitelic V8DJX232BLT/v8dj232blt ac characteristics t a = 0 c to 70 c, v cc = 5 v 10%, v ss = 0v unless otherwise noted ac test conditions, input pulse levels 0 to 3v # symbol parameter V8DJX232BLT unit notes 50 60 min. max. min. max. 1t ras ras pulse width 50 75k 60 75k ns 2t rc read or write cycle time 90 110 ns 3t rp ras precharge time 30 40 ns 4t csh cas hold time 50 60 ns 5t cas cas pulse width 9 15 ns 6t rcd ras to cas delay 19 36 20 45 ns 7t rcs read command setup time 0 0 ns 4 8t asr row address setup time 0 0 ns 9t rah row address hold time 9 10 ns 10 t asc column address setup time 0 0 ns 11 t cah column address hold time 7 10 ns 12 t rsh (r) ras hold time (read cycle) 15 15 ns 13 t crp cas to ras precharge time 5 5 ns 14 t rch read command hold time referenced to cas 0 0 ns 5 15 t rrh read command hold time referenced to ras 0 0 ns 5 16 t cac access time from cas (edo) 14 15 ns 6, 7, 14 17 t rac access time from ras 50 60 ns 6, 8, 9 18 t caa access time from column address 24 30 ns 6, 7, 10 19 t lz cas to low-z output 0 0 ns 16 20 t hz cas to high-z output 0 8 0 10 ns 16 21 t ar column address hold time from ras 40 50 ns 22 t rad ras to column address delay time 14 26 15 30 ns 11 23 t rsh (w) ras or cas hold time in write cycle 14 15 ns 24 t cwl write command to cas lead time 14 15 ns 25 t wcs write command setup time 0 0 ns 12, 13 26 t wch write command hold time 7 10 ns 27 t wp write pulse width 7 10 ns 28 t wcr write command hold time from ras 40 50 ns 29 t rwl write command to ras lead time 14 15 ns 30 t ds data in setup time 0 0 ns 14 31 t dh data in hold time 7 10 ns 14
mosel vitelic V8DJX232BLT/v8dj232blt 9 V8DJX232BLT/v8dj232blt rev. 32 t rwc (rmw) read-modify-write cycle time 130 170 ns 33 t rrw (rmw) read-modify-write cycle ras pulse width 87 105 ns 34 t cwd cas to we delay 34 40 ns 12 35 t rwd ras to we delay in read-modify-write cycle 68 85 ns 12 36 t crw cas pulse width (rmw) 52 65 ns 37 t awd col. address to we delay 42 58 ns 12 38 t pc edo page mode read or write cycle time 19 27 ns 39 t cp cas precharge time 7 10 ns 40 t car column address to ras setup time 24 30 ns 41 t cap access time from column precharge 27 34 ns 7 42 t dhr data in hold time referenced to ras 40 50 ns 43 t csr cas setup time cas -before-ras refresh 10 10 ns 44 t rpc ras to cas precharge time 0 0 ns 45 t chr cas hold time cas -before-ras refresh 12 15 ns 46 t pcm edo page mode read-modify-write cycle time 70 85 ns 47 t coh output hold after cas low 5 5 ns 48 t t transition time (rise and fall) 3 50 3 50 ns 15 49 t ref refresh interval (1024 cycles) 16 16 ms 17 # symbol parameter V8DJX232BLT unit notes 50 60 min. max. min. max.
10 V8DJX232BLT/v8dj232blt rev. 0.1 february mosel vitelic V8DJX232BLT/v8dj232blt notes: 1. i cc is dependent on output loading when the device output is selected. specified i cc (max.) is measured with the output open. 2. i cc is dependent upon the number of address transitions. specified i cc (max.) is measured with a maximum of two transitions per address cycle in edo page mode. 3. specified v il (min.) is steady state operating. during transitions, v il (min.) may undershoot to ?.0 v for a period not to exceed 20 ns. all ac parameters are measured with v il (min.) 3 v ss and v ih (max.) v cc . 4. t rcd (max.) is specified for reference only. operation within t rcd (max.) limits insures that t rac (max.) and t caa (max.) can be met. if t rcd is greater than the specified t rcd (max.), the access time is controlled by t caa and t cac . 5. either t rrh or t rch must be satisified for a read cycle to occur. 6. measured with a load equivalent to one ttl inputs and 100 pf. 7. access time is determined by the longest of t caa , t cac and t cap . 8. assumes that t rad t rad (max.). if t rad is greater than t rad (max.), t rac will increase by the amount that t rad ex- ceeds t rad (max.). 9. assumes that t rcd t rcd (max.). if t rcd is greater than t rcd (max.), t rcd will increase by the amount that t rcd exceeds t rcd (max.). 10. assumes that t rad 3 t rad (max.). 11. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, the access time is controlled by t caa and t cac . 12. t wcs , t rwd , t awd and t cwd are not restrictive operating parameters. 13. t wcs (min.) must be satisfied in an early write cycle. 14. t ds and t dh are referenced to the latter occurrence of cas or we . 15. t t is measured between v ih (min.) and v il (max.). ac-measurements assume t t = 3 ns. 16. assumes a three-state test load (5 pf and a 380 ohm thevenin equivalent). 17. an initial 200 m s pause and 8 ras -containing cycles are required when exiting an extended period of bias without clocks. an extended period of time without clocks is defined as one that exceeds the specified refresh interval.
mosel vitelic V8DJX232BLT/v8dj232blt 11 V8DJX232BLT/v8dj232blt rev. package dimensions .69 [17.53] 4.25 [107.95] 3.98 [101.19] 1.75 [44.45] .25 [6.35] 1.75 [44.45] .25 [6.35] .05 [1.27] .06 [1.57] unit in inches [mm] a detail a .40 [10.16] r = .06 [1.57] .13 [3.38] d = .12 [3.175] .08 [2.03] .04 [1] .251 [6.375] .1 [2.54] .010 [0.25]
mosel vitelic worldwide offices V8DJX232BLT/v8dj232blt ?copyright 1997, mosel vitelic inc. 2/99 printed in u.s.a. mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 u.s. sales offices the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 852-2665-4883 fax: 852-2664-7535 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 1 creation road i science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-578-3344 fax: 886-3-579-2838 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan wbg marine west 25f 6, nakase 2-chome mihama-ku, chiba-shi chiba 261-71 phone: 81-43-299-6000 fax: 81-43-299-6555 ireland & uk block a unit 2 broomfield business park malahide co. dublin, ireland phone: +353 1 8038020 fax: +353 1 8038049 germany (continental europe & israel ) 71083 herrenberg benzstr. 32 germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 southwestern suite 200 5150 e. pacific coast hwy. long beach, ca 90804 phone: 562-498-3314 fax: 562-597-2174 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341

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